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tps5410 slvs675d ? august 2006 ? revised december 2014 tps5410 1-a, wide input range, step-down converter 1 features 3 description the tps5410 is a high-output-current pwm 1 ? wide input voltage range: 5.5 v to 36 v converter that integrates a low-resistance, high-side, ? up to 1-a continuous (1.2-a peak) output current n-channel mosfet. included on the substrate with ? high efficiency up to 95% enabled by 110-m ? the listed features is a high performance voltage error integrated mosfet switch amplifier that provides tight voltage regulation accuracy under transient conditions; an undervoltage- ? wide output voltage range: adjustable down to lockout circuit to prevent start-up until the input 1.22 v with 1.5% initial accuracy voltage reaches 5.5 v; an internally set slow-start ? internal compensation minimizes external parts circuit to limit inrush currents; and a voltage feed- count forward circuit to improve the transient response. ? fixed 500-khz switching frequency for small using the ena pin, shutdown supply current is reduced to 18 a typically. other features include an filter size active high enable, overcurrent limiting, overvoltage ? improved line regulation and transient protection and thermal shutdown. to reduce design response by input voltage feed-forward complexity and external component count, the ? system protected by overcurrent limiting, tps5410 feedback loop is internally compensated. overvoltage protection and thermal shutdown the tps5410 device is available in an easy to use 8- ? ? 40 c to 125 c operating junction temperature pin soic package. ti provides evaluation modules range and software tools to aid in quickly achieving high- ? available in small 8-pin soic package performance power supply designs to meet aggressive equipment development cycles. 2 applications device information (1) ? consumer: set-top box, dvd, lcd displays part number package body size (nom) ? industrial and car audio power supplies tps5410d soic (8) 3.91 mm x 4.90 mm ? battery chargers, high-power led supply (1) for all available packages, see the orderable addendum at ? 12-v/24-v distributed power systems the end of the datasheet. 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. vinnc nc ena gnd vsense boot ph tps5410 vin vout 75 80 85 90 95 100 0 0.2 0.4 0.6 1 1.2 1.4 efficiency ? % i output current a o - - efficiency vs output current simplified schematic v i = 20 v v = 12 v f = 500 khz t = 25 c o s a o 0.8 productfolder sample &buy technical documents tools & software support &community
tps5410 slvs675d ? august 2006 ? revised december 2014 www.ti.com table of contents 7.3 feature description ................................................... 9 1 features .................................................................. 1 7.4 device functional modes ........................................ 10 2 applications ........................................................... 1 8 applications and implementation ...................... 11 3 description ............................................................. 1 8.1 application information ............................................ 11 4 revision history ..................................................... 2 8.2 typical applications ................................................ 11 5 pin configuration and functions ......................... 3 9 power supply recommendations ...................... 21 6 specifications ......................................................... 3 10 layout ................................................................... 21 6.1 absolute maximum ratings ...................................... 3 10.1 layout guidelines ................................................. 21 6.2 esd ratings .............................................................. 4 10.2 layout example .................................................... 22 6.3 recommended operating conditions ....................... 4 11 device and documentation support ................. 23 6.4 thermal information .................................................. 4 11.1 documentation support ....................................... 23 6.5 electrical characteristics ........................................... 4 11.2 trademarks ........................................................... 23 6.6 typical characteristics .............................................. 6 11.3 electrostatic discharge caution ............................ 23 7 detailed description .............................................. 8 11.4 glossary ................................................................ 23 7.1 overview ................................................................... 8 12 mechanical, packaging, and orderable 7.2 functional block diagram ......................................... 8 information ........................................................... 23 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision c (september 2013) to revision d page ? added esd ratings table, feature description section, device functional modes, application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section. ................................................................................................. 1 changes from revision b (january 2013) to revision c page ? deleted swift from the data sheet title, features , and description .................................................................................. 1 changes from revision a (november 2006) to revision b page ? replaced the dissipation ratings with the thermal information table ............................................................... 4 changes from original (august 2006) to revision a page ? changed the efficiency vs output current graph ................................................................................................................... 1 ? changed the functional block diagram ................................................................................................................................. 8 2 submit documentation feedback copyright ? 2006 ? 2014, texas instruments incorporated product folder links: tps5410
tps5410 www.ti.com slvs675d ? august 2006 ? revised december 2014 5 pin configuration and functions d package 8 pins top view pin functions pin i/o description name no. boost capacitor for the high-side fet gate driver. connect 0.01 f low esr capacitor from boot pin to boot 1 o ph pin. nc 2, 3 ? not connected internally. vsense 4 i feedback voltage for the regulator. connect to output voltage divider. ena 5 i on/off control. below 0.5 v, the device stops switching. float the pin to enable. gnd 6 ? ground. input supply voltage. bypass vin pin to gnd pin close to device package with a high quality, low esr vin 7 i ceramic capacitor. ph 8 o source of the high side power mosfet. connected to external inductor and diode. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) (2) min max unit vin ? 0.3 40 (3) ph (steady-state) ? 0.6 40 (3) en ? 0.3 7 v i input voltage range vsense ? 0.3 3 v boot-ph ? 0.3 10 ph (transient < 10 ns) ? 1.2 i o source current ph internally limited i lkg leakage current ph 10 a t j operating virtual junction temperature ? 40 150 c t stg storage temperature ? 65 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground terminal. (3) approaching the absolute maximum rating for the vin pin may cause the voltage on the ph pin to exceed the absolute maximum rating. copyright ? 2006 ? 2014, texas instruments incorporated submit documentation feedback 3 product folder links: tps5410 12 3 4 87 6 5 boot ncnc vsense phvin gnd ena
tps5410 slvs675d ? august 2006 ? revised december 2014 www.ti.com 6.2 esd ratings value unit human-body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v (esd) electrostatic discharge v charged-device model (cdm), per jedec specification jesd22- 1500 c101 (2) (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.3 recommended operating conditions min nom max unit v vin input voltage range 5.5 36 v t j operating junction temperature ? 40 125 c 6.4 thermal information tps5410 thermal metric (1) d unit 8 pins r ja junction-to-ambient thermal resistance (custom board) (2) 75 r ja junction-to-ambient thermal resistance (standard board) 105.9 r jc(top) junction-to-case (top) thermal resistance 45.0 r jb junction-to-board thermal resistance 47.8 c/w jt junction-to-top characterization parameter 5.7 jb junction-to-board characterization parameter 47.0 r jc(bot) junction-to-case (bottom) thermal resistance n/a (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . (2) test boards conditions: ( a) 3 in x 3 in, 2 layers, thickness: 0.062 inch. ( b) 2 oz. copper traces located on the top and bottom of the pcb. 6.5 electrical characteristics t j = ? 40 c to 125 c, vin = 5.5 v to 36 v (unless otherwise noted) parameter test conditions min typ max unit supply voltage (vin pin) vsense = 2 v, not switching, ph pin 3 4.4 ma open i q quiescent current shutdown, ena = 0 v 18 50 a undervoltage lock out (uvlo) start threshold voltage, uvlo 5.3 5.5 v hysteresis voltage, uvlo 330 mv voltage reference t j = 25 c 1.202 1.221 1.239 voltage reference accuracy v i o = 0 a ? 1 a 1.196 1.221 1.245 oscillator internally set free-running frequency 400 500 600 khz minimum controllable on time 150 200 ns maximum duty cycle 87% 89% enable (ena pin) start threshold voltage, ena 1.3 v stop threshold voltage, ena 0.5 v hysteresis voltage, ena 450 mv internal slow-start time (0 ~ 100%) 6.6 8 10 ms 4 submit documentation feedback copyright ? 2006 ? 2014, texas instruments incorporated product folder links: tps5410
tps5410 www.ti.com slvs675d ? august 2006 ? revised december 2014 electrical characteristics (continued) t j = ? 40 c to 125 c, vin = 5.5 v to 36 v (unless otherwise noted) parameter test conditions min typ max unit current limit current limit 1.2 1.5 1.8 a current limit hiccup time 13 16 20 ms thermal shutdown thermal shutdown trip point 135 162 c thermal shutdown hysteresis 14 c output mosfet vin = 5.5 v 150 r ds(on) high-side power mosfet switch m ? vin = 10 v - 36 v 110 230 copyright ? 2006 ? 2014, texas instruments incorporated submit documentation feedback 5 product folder links: tps5410
tps5410 slvs675d ? august 2006 ? revised december 2014 www.ti.com 6.6 typical characteristics figure 1. oscillator frequency vs junction temperature figure 2. operating quiescent current vs junction temperature figure 3. minimum controllable on time vs junction figure 4. voltage reference vs junction temperature temperature figure 5. on state resistance vs junction temperature figure 6. internal slow-start time vs junction temperature 6 submit documentation feedback copyright ? 2006 ? 2014, texas instruments incorporated product folder links: tps5410 -50 -25 0 25 125 t ? junction temperature ? c j o 100 75 50 1.22 1.23 1.225 v voltage reference ? v ref ? 1.21 1.215 1.22 1.23 1.225 v voltage reference ? v ref ? 1.21 1.215 -50 -25 0 25 125 t ? junction temperature ? c j o 100 75 50 v = 12 v i 3 3.5 3.25 i operating quiescent current ? ma q ? 2.5 2.75 460 -50 -25 0 25 125 t ? junction temperature ? c j o 100 75 50 460 470 530500 520510 f oscillator frequency ? khz ? 480 490 8 9 8.5 t internal slow start time ? ms ss ? 7 7.5 -50 -25 0 25 125 t ? junction temperature ? c j o 100 75 50 v = 12 v i -50 -25 0 25 125 t ? junction temperature ? c j o 100 75 50 80 180150 170160 r on-state resistance ? m ds(on) w ? 90 120 130 140100 110 120 180150 170160 minimum controllable on time ? ns 130 140 -50 -25 0 25 125 t ? junction temperature ? c j o 100 75 50
tps5410 www.ti.com slvs675d ? august 2006 ? revised december 2014 typical characteristics (continued) figure 8. minimum controllable duty ratio vs junction figure 7. shutdown quiescent current vs input voltage temperature copyright ? 2006 ? 2014, texas instruments incorporated submit documentation feedback 7 product folder links: tps5410 i shutdown current ? a sd m ? 25 ena = 0 v t = 125 c j o t = 27 c j o t = -40 c j o 0 40 v ? input voltage ? v i 15 10 5 5 20 15 10 20 35 30 25 7.5 8 7.5 minimum duty ratio ? % 7 7.25 -50 -25 0 25 125 t ? junction temperature ? c j o 100 75 50
tps5410 slvs675d ? august 2006 ? revised december 2014 www.ti.com 7 detailed description 7.1 overview the tps5410 is a 36-v, 1-a step-down (buck) regulator with an integrated, high-side, n-channel mosfet. these devices implement constant-frequency voltage-mode control with voltage feed-forward for improved line regulation and line transient response. internal compensation reduces design complexity and external component count. the integrated 110-m high-side mosfet supports high-efficiency power-supply designs capable of delivering 1-a of continuous current to a load. the gate-drive bias voltage for the integrated high-side mosfet is supplied by a bootstrap capacitor connected from the boot to ph pins. the tps5410 reduces the external component count by integrating the bootstrap recharge diode. the tps5410 has a default input start-up voltage of 5.3 v typical. the ena pin can be used to disable the tps5410 reducing the supply current to 18 a. an internal pullup current source enables operation when the ena pin is floating. the tps5410 includes an internal slow-start circuit that slows the output rise time during start up to reduce in rush current and output voltage overshoot. the minimum output voltage is the internal 1.221-v feedback reference. output overvoltage transients are minimized by an overvoltage protection (ovp) comparator. when the ovp comparator is activated, the high- side mosfet is turned off and remains off until the output voltage is less than 112.5% of the desired output voltage. internal cycle-by-cycle overcurrent protection limits the peak current in the integrated high-side mosfet. for continuous overcurrent fault conditions the tps5410 will enter hiccup mode overcurrent limiting. thermal protection protects the device from overheating. 7.2 functional block diagram 8 submit documentation feedback copyright ? 2006 ? 2014, texas instruments incorporated product folder links: tps5410 vin uvlo enable thermal protection reference overcurrent gate drive oscillator ramp generator vref ph ena gnd shdn shdn boot z1 z2 shdn shdn shdn shdn vin shdn hiccup hiccup shdn shdn nc feed forward boot nc vin vout 5 a 1.221 v bandgap slow start boot regulator error amplifier gain = 25 pwm comparator protection gatedriver control vsense 112.5% vref vsense ovp
tps5410 www.ti.com slvs675d ? august 2006 ? revised december 2014 7.3 feature description 7.3.1 oscillator frequency the internal free running oscillator sets the pwm switching frequency at 500 khz. the 500-khz switching frequency allows less output inductance for the same output ripple requirement resulting in a smaller output inductor. 7.3.2 voltage reference the voltage reference system produces a precision reference signal by scaling the output of a temperature stable bandgap circuit. the bandgap and scaling circuits are trimmed during production testing to an output of 1.221 v at room temperature. 7.3.3 enable (ena) and internal slow-start the ena pin provides electrical on/off control of the regulator. once the ena pin voltage exceeds the threshold voltage, the regulator starts operation and the internal slow-start begins to ramp. if the ena pin voltage is pulled below the threshold voltage, the regulator stops switching and the internal slow-start resets. connecting the pin to ground or to any voltage less than 0.5 v disables the regulator and activate the shutdown mode. the quiescent current of the tps5410 in shutdown mode is typically 18 a. the ena pin has an internal pullup current source, allowing the user to float the ena pin. if an application requires controlling the ena pin, use open drain or open collector output logic to interface with the pin. to limit the start-up inrush current, an internal slow-start circuit is used to ramp up the reference voltage from 0 v to its final value linearly. the internal slow-start time is 8 ms typically. 7.3.4 undervoltage lockout (uvlo) the tps5410 incorporates an undervoltage lockout circuit to keep the device disabled when vin (the input voltage) is below the uvlo start voltage threshold. during power up, internal circuits are held inactive and the internal slow-start is grounded until vin exceeds the uvlo start threshold voltage. once the uvlo start threshold voltage is reached, the internal slow-start is released and device start-up begins. the device operates until vin falls below the uvlo stop threshold voltage. the typical hysteresis in the uvlo comparator is 330 mv. 7.3.5 boost capacitor (boot) connect a 0.01- f low-esr ceramic capacitor between the boot pin and ph pin. this capacitor provides the gate drive voltage for the high-side mosfet. x7r or x5r grade dielectrics are recommended due to their stable values over temperature. 7.3.6 output feedback (vsense) the output voltage of the regulator is set by feeding back the center point voltage of an external resistor divider network to the vsense pin. in steady-state operation, the vsense pin voltage should be equal to the voltage reference 1.221 v. 7.3.7 internal compensation the tps5410 implements internal compensation to simplify the regulator design. since the tps5410 uses voltage mode control, a type 3 compensation network has been designed on chip to provide a high crossover frequency and a high phase margin for good stability. see the internal compensation network in the applications section for more details. 7.3.8 voltage feed-forward the internal voltage feed-forward provides a constant dc power stage gain despite any variations with the input voltage. this greatly simplifies the stability analysis and improves the transient response. voltage feed-forward varies the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain are constant at the feed-forward gain, for example: (1) the typical feed-forward gain of tps5410 is 25. copyright ? 2006 ? 2014, texas instruments incorporated submit documentation feedback 9 product folder links: tps5410 feed forward gain = vin ramp pk-pk
tps5410 slvs675d ? august 2006 ? revised december 2014 www.ti.com feature description (continued) 7.3.9 pulse-width-modulation (pwm) control the regulator employs a fixed frequency pulse-width-modulator (pwm) control method. first, the feedback voltage (vsense pin voltage) is compared to the constant voltage reference by the high gain error amplifier and compensation network to produce a error voltage. then, the error voltage is compared to the ramp voltage by the pwm comparator. in this way, the error voltage magnitude is converted to a pulse width which is the duty cycle. finally, the pwm output is fed into the gate drive circuit to control the on-time of the high-side mosfet. 7.3.10 overcurrent liming overcurrent limiting is implemented by sensing the drain-to-source voltage across the high-side mosfet. the drain to source voltage is then compared to a voltage level representing the overcurrent threshold limit. if the drain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. the system will ignore the overcurrent indicator for the leading edge blanking time at the beginning of each cycle to avoid any turn-on noise glitches. once overcurrent indicator is set true, overcurrent limiting is triggered. the high-side mosfet is turned off for the rest of the cycle after a propagation delay. the overcurrent limiting scheme is called cycle-by-cycle current limiting. sometimes under serious overload conditions such as short-circuit, the overcurrent runaway may still happen when using cycle-by-cycle current limiting. a second mode of current limiting is used, for example hiccup mode overcurrent limiting. during hiccup mode overcurrent limiting, the voltage reference is grounded and the high-side mosfet is turned off for the hiccup time. once the hiccup time duration is complete, the regulator restarts under control of the slow-start circuit. 7.3.11 overvoltage protection the tps5410 has an overvoltage protection (ovp) circuit to minimize voltage overshoot when recovering from output fault conditions. the ovp circuit includes an overvoltage comparator to compare the vsense pin voltage and a threshold of 112.5% x vref. once the vsense pin voltage is higher than the threshold, the high-side mosfet will be forced off. when the vsense pin voltage drops lower than the threshold, the high-side mosfet will be enabled again. 7.3.12 thermal shutdown the tps5410 protects itself from overheating with an internal thermal shutdown circuit. if the junction temperature exceeds the thermal shutdown trip point, the voltage reference is grounded and the high-side mosfet is turned off. the part is restarted under control of the slow-start circuit automatically when the junction temperature drops 14 c below the thermal shutdown trip point. 7.4 device functional modes 7.4.1 minimum input voltage confid the tps5410 is recommended to operate with input voltages above 5.5 v. the typical vin uvlo threshold is 5.3 v and the device may operate at input voltages down to the uvlo voltage. at input voltages below the actual uvlo voltage the device will not switch. if ena is floating or externally pulled up to greater up than 1.3 v, when v (vin) passes the uvlo threshold the tps5410 will become active. switching is enabled and the slow-start sequence is initiated. the tps5410 starts linearly ramping up the internal reference voltage from 0 v to its final value over the internal slow-start time period. 7.4.2 ena control t the enable start threshold voltage is 1.3 v max. with ena held below the 0.5 v minimum stop threshold voltage the tps5410 is disabled and switching is inhibited even if vin is above its uvlo threshold. the quiescent current is reduced in this state. if the ena voltage is increased above the max start threshold while v (vin) is above the uvlo threshold, the device becomes active. switching is enabled and the slow-start sequence is initiated. the tps5410 starts linearly ramping up the internal reference voltage from 0 v to its final value over the internal slow-start time period. 10 submit documentation feedback copyright ? 2006 ? 2014, texas instruments incorporated product folder links: tps5410
tps5410 www.ti.com slvs675d ? august 2006 ? revised december 2014 8 applications and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the tps5410 is a 1-a, step down regulator with an integrated high-side mosfet. this device is typically used to convert a higher dc voltage to a lower dc voltage with a maximum available output current of 1 a. example applications are: high density point-of-load regulators for set-top box, dvd, lcd and plasma displays, high power led supply, car audio, battery chargers, and other 12-v and 24-v distributed power systems. use the following design procedure to select component values for the tps5410. this procedure illustrates the design of a high frequency switching regulator. alternatively, use the webench software to generate a complete design. the webench software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. 8.2 typical applications 8.2.1 application circuit figure 9 shows the schematic for a typical tps5410 application. the tps5410 can provide up to 1-a output current at a nominal output voltage of 12 v. a. c3 = tantalum avx tpse476m020r0150 figure 9. application circuit, 14.5-v ? 36 v to 12-v copyright ? 2006 ? 2014, texas instruments incorporated submit documentation feedback 11 product folder links: tps5410 gnd vsns vin nc nc ena boot ph vin u1 tps5410d 12 v 14.5 v 36 v - c1 4.7 f m c3 47 f (see note a) m c2 0.01 f m l1 68 h m r21.13 k w d1 b340a 7 1 5 8 2 4 3 6 vout ena + r110 k w
tps5410 slvs675d ? august 2006 ? revised december 2014 www.ti.com typical applications (continued) 8.2.1.1 design requirements for this design example, use the following as the input parameters: table 1. design requirements design parameter (1) example value input voltage range 14.5 v to 36 v output voltage 12 v input ripple voltage 300 mv output ripple voltage 50 mv output current rating 1 a operating frequency 500 khz (1) as an additional constraint, the design is set up to be small size and low component height. 8.2.1.2 detailed design procedure 8.2.1.2.1 switching frequency the switching frequency for the tps5410 is internally set to 500 khz. it is not possible to adjust the switching frequency. 8.2.1.2.2 input capacitors the tps5410 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor. the minimum recommended value for the decoupling capacitor is 4.7 f. a high quality ceramic type x5r or x7r is required. for some applications, a smaller value decoupling capacitor may be used, if the input voltage and current ripple ratings are not exceeded. the voltage rating must be greater than the maximum input voltage, including ripple. for this design, a 4.7 f capacitor, c1 issued to allow for smaller 1812 case size to be used while maintaining a 50 v rating. this input ripple voltage can be approximated by equation 2 : (2) where i out(max) is the maximum load current, f sw is the switching frequency, c i is the input capacitor value and esr max is the maximum series resistance of the input capacitor. the maximum rms ripple current also needs to be checked. for worst case conditions, this is approximated by equation 3 : (3) in this example, the calculated input ripple voltage is 137 mv, and the rms ripple current is 0.5 a. the maximum voltage across the input capacitors would be vin max plus delta vin/2. the chosen input decoupling capacitors are rated for 50 v, and the ripple current capacity for each is 3 a at 500 khz, providing ample margin. the actual measured input ripple voltage may be larger than the calculated value due to the output impedance of the input voltage source, decrease in actual capacitance due to bias voltage and parasitics associated with the layout. caution the maximum ratings for voltage and current are not to be exceeded under any circumstance. 12 submit documentation feedback copyright ? 2006 ? 2014, texas instruments incorporated product folder links: tps5410 i cin i out(max) 2 d v in = ( ) i out(max) x 0.25 + i out(max) max x esr c bulk sw x ?
tps5410 www.ti.com slvs675d ? august 2006 ? revised december 2014 additionally, some bulk capacitance may be needed, especially if the tps5410 circuit is not located within approximately 2 inches from the input voltage source. the value for this capacitor is not critical but it should be rated to handle the maximum input voltage including ripple voltage and should filter the output so that input ripple voltage is acceptable. 8.2.1.2.3 output filter components two components need to be selected for the output filter, l1 and c3. since the tps5410 is an internally compensated device, a limited range of filter component types and values can be supported. 8.2.1.2.3.1 inductor selection to calculate the minimum value of the output inductor, use equation 4 : (4) k ind is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. three things need to be considered when determining the amount of ripple current in the inductor: the peak to peak ripple current affects the output ripple voltage amplitude, the ripple current affects the peak switch current, and the amount of ripple current determines at what point the circuit becomes discontinuous. for designs using the tps5410, k ind of 0.2 to 0.3 yields good results. low output ripple voltages is obtained when paired with the proper output capacitor, the peak switch current is below the current limit set point, and low load currents can be sourced before discontinuous operation. for this design example, use k ind = 0.3, and the minimum inductor value is 66 h. the next highest standard value used in this design is 68 h. for the output filter inductor, it is important that the rms current and saturation current ratings not be exceeded. the rms inductor current can be found from equation 5 : (5) and the peak inductor current can be determined using equation 6 : (6) for this design, the rms inductor current is 1.004 a, and the peak inductor current is 1.147 a. the chosen inductor is a coilcraft mss1260-683 type. the nominal inductance is 68 h. it has a saturation current rating of 2.3 a and a rms current rating of 2.3 a, which meets the requirements. inductor values for use with the tps5410 are in the range of 10 h to 100 h. 8.2.1.2.3.2 capacitor selection the important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent series resistance (esr). the dc voltage and ripple current ratings cannot be exceeded. the esr is important because along with the inductor ripple current it determines the amount of output ripple voltage. the actual value of the output capacitor is not critical, but some practical limits do exist. consider the relationship between the desired closed loop crossover frequency of the design and lc corner frequency of the output filter. due to the design of the internal compensation, it is recommended to keep the closed loop crossover frequency in the range 3 khz to 30 khz as this frequency range has adequate phase boost to allow for stable operation. for this design example, the intended closed loop crossover frequency is between 2590 hz and 24 khz, and below the esr zero of the output capacitor. under these conditions, the closed loop crossover frequency is related to the lc corner frequency as: (7) copyright ? 2006 ? 2014, texas instruments incorporated submit documentation feedback 13 product folder links: tps5410 i l(pk) = i + out(max) ( ) v v v out in(max) out x - 1.6 x v x l x f in(max) out sw i l(rms) i 2 out(max) 1 12 v out v in(max) v out v in(max) l out f sw 0.8 2 l min = ( ) v out in(max) out x v - v v in(max) ind out sw x k x i x f x 0.8 f co f lc 2 85 v out
tps5410 slvs675d ? august 2006 ? revised december 2014 www.ti.com and the desired output capacitor value for the output filter to: (8) for a desired crossover of 10 khz and a 68- h inductor, the calculated value for the output capacitor is 36.5 f. the capacitor type should be chosen so that the esr zero is above the loop crossover. the maximum esr is: (9) the maximum esr of the output capacitor also determines the amount of output ripple as specified in the initial design parameters. the output ripple voltage is the inductor ripple current times the esr of the output filter. check that the maximum specified esr as listed in the capacitor data sheet results in an acceptable output ripple voltage: (10) where: v pp is the desired peak-to-peak output ripple. n c is the number of parallel output capacitors. f sw is the switching frequency. the minimum esr of the output capacitor should also be considered. for a good phase margin, if the esr is zero when the esr is at its minimum, it should not be above the internal compensation poles at 24 khz and 54 khz. the selected output capacitor must also be rated for a voltage greater than the desired output voltage plus one half the ripple voltage. any derating amount must also be included. the maximum rms ripple current in the output capacitor is given by equation 11 : (11) where: n c is the number of output capacitors in parallel. f sw is the switching frequency. for this design example, a single 47- f output capacitor is chosen for c3. this value is close to the calculated value of 36.5 f and yields an actual closed loop cross over frequency of 10.05 khz. the calculated rms ripple current is 84.9 ma and the maximum esr required is 339 m ? . a capacitor that meets these requirements is a avx tpse476m020r0150, rated at 20 v with a maximum esr of 150 m ? and a ripple current rating of 1.369 a. this capacitor results in a peak-to-peak output ripple of 44 mv using equation 10. an additional small 0.1- f ceramic bypass capacitor may also used, but is not included in this design. other capacitor types can be used with the tps5410, depending on the needs of the application. 8.2.1.2.4 output voltage setpoint the output voltage of the tps5410 is set by a resistor divider (r1 and r2) from the output to the vsense pin. calculate the r2 resistor value for the output voltage of 12 v using equation 12 : (12) for any tps5410 design, start with an r1 value of 10 k ? . r2 is then 1.13 k ? . 8.2.1.2.5 boot capacitor the boot capacitor should be 0.01 f. 14 submit documentation feedback copyright ? 2006 ? 2014, texas instruments incorporated product folder links: tps5410 r2 r1 1.221 v out 1.221 1 x i cout(rms) = ? 12 [ ] v out in(max) out x v - v v in(max) out sw x l - f x 0.8 x n c ( ) v pp (max) = ( ) esr x v v v max out in(max) out x - n c in(max) out sw x v x l x f x 0.8 esr max 1 2 c out f co c out 1 3357 l out f co v out
tps5410 www.ti.com slvs675d ? august 2006 ? revised december 2014 8.2.1.2.6 catch diode the tps5410 is designed to operate using an external catch diode between ph and gnd. the selected diode must meet the absolute maximum ratings for the application: reverse voltage must be higher than the maximum voltage at the ph pin, which is vinmax + 0.5 v. peak current must be greater than ioutmax plus on half the peak-to-peak inductor current. forward voltage drop should be small for higher efficiencies. it is important to note that the catch diode conduction time is typically longer than the high-side fet on time; therefore, the diode parameters improve the overall efficiency. additionally, check that the device chosen is capable of dissipating the power losses. for this design, a diodes, inc. b340a is chosen, with a reverse voltage of 40 v, forward current of 3 a, and a forward voltage drop of 0.5 v. 8.2.1.2.7 advanced information 8.2.1.2.7.1 output voltage limitations due to the internal design of the tps5410, there are both upper and lower output voltage limits for any given input voltage. the upper limit of the output voltage set point is constrained by the maximum duty cycle of 87% and is given by: (13) where: v inmin = minimum input voltage i omax = maximum load current v d = catch diode forward voltage. r l = output inductor series resistance. this equation assumes maximum on resistance for the internal high side fet. the lower limit is constrained by the minimum controllable on time which may be as high as 200 ns. the approximate minimum output voltage for a given input voltage and minimum load current is given by: (14) where: v inmax = maximum input voltage i omin = minimum load current v d = catch diode forward voltage. r l = output inductor series resistance. this equation assumes nominal on resistance for the high side fet and accounts for worst case variation of operating frequency set point. any design operating near the operational limits of the device should be checked to assure proper functionality. 8.2.1.2.7.2 internal compensation network the design equations given in the example circuit can be used to generate circuits using the tps5410. these designs are based on certain assumptions, and always select output capacitors within a limited range of esr values. if a different capacitor type is desired, it may be possible to fit one to the internal compensation of the tps5410. equation 15 gives the nominal frequency response of the internal voltage-mode type iii compensation network: (15) where fp0 = 2165 hz, fz1 = 2170 hz, fz2 = 2590 hz fp1 = 24 khz, fp2 = 54 khz, fp3 = 440 khz fp3 represents the non-ideal parasitics effect. copyright ? 2006 ? 2014, texas instruments incorporated submit documentation feedback 15 product folder links: tps5410 h(s) 1 s 2 fz1 1 s 2 fz2 s 2 fp0 1 s 2 fp1 1 s 2 fp2 1 s 2 fp3 v outmin 0.12 v inmax i omin 0.110 v d i omin r l v d v outmax 0.87 v inmin i omax 0.230 v d i omax r l v d
tps5410 slvs675d ? august 2006 ? revised december 2014 www.ti.com using this information along with the desired output voltage, feed-forward gain and output filter characteristics, the closed loop transfer function can be derived. 8.2.1.2.7.3 thermal calculations the following formulas show how to estimate the device power dissipation under continuous conduction mode operations. they should not be used if the device is working at light loads in the discontinuous conduction mode. conduction loss: pcon = i out 2 x rds(on) x v out / v in switching loss: psw = v in x i out x 0.01 quiescent current loss: pq = v in x 0.01 total loss: ptot = pcon + psw + pq given t a = > estimated junction temperature: t j = t a + rth x ptot given t jmax = 125 c = > estimated maximum ambient temperature: t amax = t jmax ? rth x ptot 8.2.1.3 application curves the performance graphs in figure 10 to figure 17 are applicable to the circuit in figure 9 . t a = 25 c. unless otherwise specified. figure 10. efficiency vs. output current figure 11. output voltage regulation % vs. output current figure 13. input voltage ripple and ph node, i o = 1 a figure 12. output voltage regulation % vs. input voltage 16 submit documentation feedback copyright ? 2006 ? 2014, texas instruments incorporated product folder links: tps5410 26 16 -0.03 -0.02 0.01 0.02 0.03 0 20 24 34 28 36 v - input voltage - v i output voltage regulation - % -0.01 32 14 18 22 30 i = 0.5 a o i = 0 a o i = 1 a o t - time - 1 s / div m v = 100 mv/div (ac coupled) in v = 10 v/div (ph) ac coupled20 mhz bwl 0.6 0 -0.03 -0.02 0.01 0.02 0.03 0 0.2 0.4 1 0.8 1.2 i - output current - a o output voltage regulation - % -0.01 v = 14.5 v i v = 20 v i v = 30 v i v = 25 v i v = 36 v i 75 80 85 90 95 100 i - output current - a o efficiency - % 0.6 0 0.2 0.4 1 0.8 1.2 1.4 v = 30 v i v = 35 v i v = 20 v i v = 14.5 v i v = 25 v i
tps5410 www.ti.com slvs675d ? august 2006 ? revised december 2014 figure 14. output voltage ripple and ph node, i o = 1 a figure 15. transient response, i o step 0.25 to 0.75 a figure 16. startup waveform, v i and v o figure 17. startup waveform, ena and v o copyright ? 2006 ? 2014, texas instruments incorporated submit documentation feedback 17 product folder links: tps5410 t - time - 5 ms / div v = 5 v/div o v = 10 v/div i t - time - 5 ms / div v = 5 v/div o ena = 2 v/div t - time - 1 s / div m v = 20 mv/div (ac coupled) in v = 10 v/div (ph) ac coupled20 mhz bwl t - time - 200 s / div m i = 500 ma/div o v = 100 mv/div o ac coupled20 mhz bwl
tps5410 slvs675d ? august 2006 ? revised december 2014 www.ti.com 8.2.2 using all ceramic capacitors figure 18 shows an application circuit using all ceramic capacitors for the input and output filters. the design procedure is similar to those given for the design example, except for the selection of the output filter capacitor values and the design of the additional compensation components required to stabilize the circuit. a. c3, c4 = ceramic tdkc4532x5r1a476mt figure 18. 7-v ? 36-v input to 5-v output application circuit with ceramic capacitors 8.2.2.1 design requirements for this design example, use table 1 as the input parameters. 8.2.2.2 detailed design procedure 8.2.2.2.1 output filter capacitor selection when using ceramic output filer capacitors, the recommended lc resonant frequency should be no more than 7 khz. since the output inductor is already selected at 68 h, this limits the minimum output capacitor value to: (16) the minimum capacitor value is calculated to be 7.6 f. for this circuit a larger value of capacitor will yield better transient response. two output capacitors are used for c3 and c4 with a value of 47 uf each. it is important to note that the actual capacitance of ceramic capacitors decreases with applied voltage. in this case the effective value used for the calculations is approximately 70 % of the rated value or 70 f. 8.2.2.2.2 external compensation network when using ceramic output capacitors, additional circuitry is required to stabilize the closed loop system. for this circuit the external components are r3, c5, c6 and c7. to determine the value of these components, first calculate the lc resonant frequency of the output filter: (17) for this example the effective resonant frequency is calculated as 2306 hz the network composed of r1, r2, r3, c5, c6 and c7 has two poles and two zeros that are used to tailor the overall response of the feedback network to accommodate the use of the ceramic output capacitors. the pole and zero locations are given by the following equations: (18) 18 submit documentation feedback copyright ? 2006 ? 2014, texas instruments incorporated product folder links: tps5410 gnd vsns vin nc nc ena boot ph vin u1 tps5410d 5 v 7 v 36 v - c1 4.7 f m c4 47 f m (note a) c2 0.01 f m l1 68 h m r23.24 k w d1 b340a 7 1 5 8 2 4 3 6 vout ena r110 k w r31.78 k w c62700 pf c5 150 pf c7 0.056 f m c3 47 f m (note a) fp1 = 500000 x v o f lc f = lc 1 2 l p o o x c (eff) ? c (min) o 3 1 2 (2 x 7000) x l p o
tps5410 www.ti.com slvs675d ? august 2006 ? revised december 2014 (19) (20) the final pole is located at a frequency too high to be of concern. the values for r1 and r2 are fixed by the 5-v output voltage as calculated using equation 12 . now the values of r3, c5, c6 and c7 are determined using equation 21 , equation 22 , and equation 23 : (21) (22) (23) for this design, using the closest standard values, c7 is 0.056 f, r3 is 1.76 k ? and c6 is 2700 pf. c5 is added to improve load regulation performance. it is effectively in parallel with c6 in the location of the second pole frequency, so it should be small in relationship to c6. c5 should be less the 1/10 the value of c6. for this example, 150 pf works well. for additional information on external compensation of the tps5410 or other wide voltage range devices, see using tps5410/20/30/31 with aluminum/ceramic output capacitors , slva237 . 8.2.2.3 application curves the performance graphs in figure 19 to figure 24 are applicable to the circuit in figure 18 . t a = 25 c. unless otherwise specified. figure 19. efficiency vs. output current figure 20. output voltage regulation % vs. output current copyright ? 2006 ? 2014, texas instruments incorporated submit documentation feedback 19 product folder links: tps5410 0.6 0 -0.1 -0.08 0.04 0.08 0.1 0 0.2 0.4 1 0.8 1.2 i - output current - a o output voltage regulation - % -0.02 -0.06 0.02 0.06 -0.04 v = 10 v i v = 15 v i v = 7 v i v = 20 v i v = 25 v i v = 30 v i v = 36 v i 75 80 85 90 95 100 i - output current - a o efficiency - % 0.6 0 0.2 0.4 1 0.8 1.2 1.4 v = 35 v i v = 20 v i v = 7 v i v = 25 v i v = 30 v i v = 10 v i v = 15 v i c6 = 1 2 x fz2 x r1 p r3 = 1 2 x fz1 x c7 p c7 = 1 2 x fp1 x (r1 || r2) p fz2 = 2.5 x f lc fz1 = 0.7 x f lc
tps5410 slvs675d ? august 2006 ? revised december 2014 www.ti.com figure 22. input voltage ripple and ph node, i o = 1 a figure 21. output voltage regulation % vs. input voltage figure 24. transient response, i o step 0.25 to 0.75 a figure 23. output voltage ripple and ph node, i o = 1 a 20 submit documentation feedback copyright ? 2006 ? 2014, texas instruments incorporated product folder links: tps5410 t - time - 1 s / div m v = 100 mv/div (ac coupled) in v = 10 v/div (ph) ac coupled20 mhz bwl t - time - 1 s / div m v = 20 mv/div (ac coupled) in v = 10 v/div (ph) ac coupled20 mhz bwl t - time - 200 s / div m i = 500 ma/div o v = 100 mv/div o ac coupled20 mhz bwl 26 16 -0.03 -0.02 0.01 0.02 0.03 0 20 24 34 28 36 v - input voltage - v i output voltage regulation - % -0.01 32 14 18 22 30 i = 0.5 a o i = 0 a o i = 1 a o
tps5410 www.ti.com slvs675d ? august 2006 ? revised december 2014 9 power supply recommendations the tps5410 is designed to operate from an input voltage supply range between 5.5 v and 36 v. this input supply should remain within the input voltage supply range. if the input supply is located more than a few inches from the tps5410 converter bulk capacitance may be required in addition to the ceramic bypass capacitors. an electrolytic capacitor with a value of 100 f is a typical choice. 10 layout 10.1 layout guidelines connect a low esr ceramic bypass capacitor to the vin pin. care should be taken to minimize the loop area formed by the bypass capacitor connections, the vin pin, and the tps5410 ground pin. the best way to do this is to extend the top side ground area from under the device adjacent to the vin trace, and place the bypass capacitor as close as possible to the vin pin. the minimum recommended bypass capacitance is 4.7 f ceramic with a x5r or x7r dielectric. there should be a ground area on the top layer directly underneath the ic to connect the gnd pin of the device and the anode of the catch diode. the gnd pin should be tied to the pcb ground by connecting it to the ground area under the device as shown in figure 25 . the ph pin should be routed to the output inductor, catch diode and boot capacitor. since the ph connection is the switching node, the inductor should be located close to the ph pin, and the area of the pcb conductor minimized to prevent excessive capacitive coupling. the catch diode should also be placed close to the device to minimize the output current loop area. connect the boot capacitor between the phase node and the boot pin as shown. keep the boot capacitor close to the ic and minimize the conductor trace lengths. the component placements and connections shown work well, but other connection routings may also be effective. connect the output filter capacitor(s) as shown between the vout trace and gnd. it is important to keep the loop formed by the ph pin, lout, cout and gnd as small as is practical. connect the vout trace to the vsense pin using the resistor divider network to set the output voltage. do not route this trace too close to the ph trace. due to the size of the ic package and the device pinout, the trace may need to be routed under the output capacitor. the routing may be done on an alternate layer if a trace under the output capacitor is not desired. if the grounding scheme shown is used via a connection to a different layer to route to the ena pin. copyright ? 2006 ? 2014, texas instruments incorporated submit documentation feedback 21 product folder links: tps5410
tps5410 slvs675d ? august 2006 ? revised december 2014 www.ti.com 10.2 layout example figure 25. design layout figure 26. tps5410 land pattern 22 submit documentation feedback copyright ? 2006 ? 2014, texas instruments incorporated product folder links: tps5410 all dimensions in inches 0.220 0.050 0.026 0.080 bootnc nc vsense ph vin gnd ena vout ph vin topside ground area via to ground plane output inductor output filter capacitor boot capacitor input bypass capacitor inputbulk filter catch diode signal via route feedbacktrace under the output filter capacitor or on the other layer. resistor divider
tps5410 www.ti.com slvs675d ? august 2006 ? revised december 2014 11 device and documentation support 11.1 documentation support 11.1.1 related documentation using tps5410/20/30/31/50 with aluminum/ceramic output capacitors , application report, slva237 11.2 trademarks all trademarks are the property of their respective owners. 11.3 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.4 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. copyright ? 2006 ? 2014, texas instruments incorporated submit documentation feedback 23 product folder links: tps5410
package option addendum www.ti.com 15-apr-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples hpa00568dr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 tps5410 tps5410d active soic d 8 75 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 tps5410 tps5410dg4 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 tps5410 tps5410dr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 tps5410 tps5410drg4 active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 tps5410 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device.
package option addendum www.ti.com 15-apr-2017 addendum-page 2 (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of tps5410 : ? automotive: tps5410-q1 ? enhanced product: TPS5410-EP note: qualified version definitions: ? automotive - q100 devices qualified for high-reliability automotive applications targeting zero defects ? enhanced product - supports defense, aerospace and medical applications
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tps5410dr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 package materials information www.ti.com 4-nov-2014 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) tps5410dr soic d 8 2500 367.0 367.0 35.0 package materials information www.ti.com 4-nov-2014 pack materials-page 2

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own risk. designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. designer will fully indemnify ti and its representatives against any damages, costs, losses, and/or liabilities arising out of designer ? s non- compliance with the terms and provisions of this notice. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2017, texas instruments incorporated

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